China’s push for chip independence continues with its first RISC-V server CPU
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CPI per CPI... RISC, but thats a trap of a question and you know it
tons of variables in that question, but there should be more headroom in RISC designs and thats why, internally, most things are RISC-y.
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this is so deliciously and disappointingly true.
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Their x86 fabs are producing a 5 yr old Intel node, and with unknown defect rate. This is about getting down to the modern node size to (eventually) to get competitive with the two major ARM nodes.
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Another example would be Home Assistant. Why exactly should my device have to connect to the internet and communicate with a cloud server somewhere that can be shut down only to communicate with my phone back at my house? With Home Assistant, my device communicates locally with my Home Assistant device and my Home Assistant device communicates locally with my phone. No internet required.
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Wow, all the down votes. Youngin's don't know what they're missing. Classic film.
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Any benchmarks? Seems like it bundles NN acceleration that competes with GPUs, but benchmarks/price matters.
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ok. my apologizes.
there really are tons of things to consider with that question. RISC has historically allowed for faster clocking and fewer cycles per instruction, so thats a win. RISC also requires more instructions per useful operation and also blows up the binary size, so...
all things being equal (hahaha) RISC has more headroom and legroom for future improvements that dont complecate the silicon to extreme degrees. the vast majority of CISC designs are now pretty RISC-like at their cores, but the software interface remains CISC and, I think, complicates and limits variety and advancement.
imho, a properly spec'd RISC processor and a carefully designed compiler, cycle for cycle, macro for macro and watt for watt outperforms a CISC design (even with a RISC-like core). major computing holy wars are been waged over this for decades.
all I currently have access to are older studies that show mixed general purpose results on RISC vs CISC (performance, not power efficiency), but if I had to make a choice about what my future ideal processor would be, it would be RISC core and RISC instruction set architecture simply due to less complexity, more efficient use of wafer space and lower power requirements. then we start talking about massively parallel RISC in tiny spaces and, for many (but not all) workloads, thats a big win.
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I mean, it's obviously the price that pushed Android to where it is today.
The fact is, you can buy some models of Android phones (new) for under $75. This makes smart phones affordable even in developing countries. That fact has sent the number of smart phones in people's hands through the roof. And honestly, part of what makes them cheap to manufacture is in fact that FLOSS base, allowing any company to develop one.
